An important trend in the electronics industry today is the use of multi-chip modules (MCMs). Simply defined, a MCM has multiple integrated circuits (ICs) packaged on an insulting substrate that interconnects the ICs and provides external connections. MCMs create functional islands using both custom and standard chips that can help provide improved system performance and smaller size and weight, while offering a cost-effective solution for many applications.
One example of a high-performance MCM multichip substrate is the IBM Corporation S/390™ product line. FIGS. 1 and 2 illustrate both form-factor and design information on one embodiment 102 of an S/390 MCM. The MCM 102 comprises a plurality of individual chips 110. The chips 110 are formed through a multilayer thick-film technology with a glass-ceramic/copper-metallurgy system. Top surface metallurgy (TSM) “Control Collapse Chip Connection” (C4) pads 124 are arrayed on a top surface 104 of the chip 110. Copper conductors 120 are utilized to form circuitry within the chips 110, said conductors 120 connected to the TSM C4 pads 124 and to bottom surface metallurgy (BSM) I/O pads 122 on the bottom surface 106 on the MCM 102.
The build process for these MCM substrates 102 is highly complex, and electrical testing is performed at several points during the fabrication sequence to minimize the capture time for the detection of unrepairable defects, to drive repair actions, and for the assurance of outgoing-part quality. It is known in the prior art to use capacitive and/or resistive techniques to detect line and via opens and shorts between MCM features. One example is the IBM Corporation-developed electronic module test (EMT™) methodology is used to screen substrates for such latent defects as line neckdowns and via abnormalities, which could lead to opens when used in the field. One means for performing capacitive or resistive test methodology is by using “Step-and-Repeat Cluster-Probe” tester architecture.
FIGS. 3 and 4 provide an illustration of a typical prior art step and repeat cluster probe tester apparatus 200, wherein two buckling beam cluster probe arm testers 202 are used to “step” onto each chip 110 of the MCM 102. A pogo-pin array 212 is brought into electrical contact with the BSM I/O pads 122 of the MSM substrate 110. The two buckling-beam probe arms 202 have a footprint that matches or partially matches with the top surface 104 of each chip 110. Each cluster probe arm 202 has a plurality of “buckling beam” probes 304, wherein each TSM C4 pad 124 is brought into compressive contact with a buckling beam probe 304. The cluster probe tester apparatus 200 control system 204 then indicates a series of tests according to its “tool application program” (TAP). Net (electrical-circuit) configurations are programmed, and testing is executed by the control system 204 via the use of a commercial switching matrix and test engine. The test is highly efficient, with thousands of net tests being executed during one probe move. When a series of tests are complete, the probe arms 202 “step” over to another chip 110 and “repeats” the same test sequence for that chip 110.
However, prior art step-and-repeat cluster-probe testing efficiency has limitations. This mode of testing requires a repeatable C4 pattern that can be stepped with a fixed pad pitch at the level being tested with limits on subfield adjacency to allow for the cluster-probe-beam support structure. As conventionally used in the computer device industry, the term “pitch” refers to the distribution within an array of commonly spaced contact pads or clustered test probes: for example, a “10 mil pitch” may refer to an array of pads with adjacent pads spaced 10 mils from each other, wherein the 10 mil spacing may be specified as a center-to-center spacing or side-to-side spacing dimension. As it is common and desirable for an MCM to comprise chips with a plurality of divergent C4 patterns and/or footprint dimensions, the prior art cluster probe tester cannot efficiently test many MCM's.
Specifically, where smaller footprint chips reside with larger footprint chips on the same MCM, a prior art step-and-repeat probe must cover the larger footprint as a minimum test footprint, which is then repeated for each chip on the MCM regardless of footprint size. Thus when the cluster probe tester tests the smaller footprint some tester contacts are driven into contact with surrounding non-circuitized substrate, or with surrounding circuitry beyond the smaller chip footprint. These surrounding regions commonly have surface depth dimensions divergent from that of the chip, which may cause failure of the cluster probe to correctly interface the chip C4 pads, may cause damage to the surrounding substrate, or may cause the creation of residual debris by an extra the interaction of probe beams with the MCM on smaller chip sites. The removal of residual debris is a significant and expensive problem for large-scale MCM production.
Prior art methods for testing MCM's that have non steppable C4 pattern include “Full Cluster Probe Test” and “Flying Probe Test methods.” The Full Cluster Probe Test uses a probe that covers the entire MCM surface C4 pattern comprising all of the chips at once and performs a single step test. This is a high throughput electrical test method, but it requires a huge resource investment on tester and probe. One exemplary MCM may require a probe with approximately 50,000 points and a series of automatic micro adjustment mechanisms. The product-specific manufacturing costs for such a full cluster probe test is enormous, perhaps in the neighborhood of five to six million dollars, and therefore not practical.
The Flying Probe Test tests one net at a time, wherein a single test probe is positioned by a precision x,y table and is put in contact with the MCM C4 pads via a z-motion actuation. This method is most appropriate for latent defect testing of glass-ceramic and thin-film wiring using EMT electronics and for opens/shorts testing at levels in thin films where product design features do not allow cluster probing or for high volume products. Advantages include the absence of significant product-specific fit-up costs and minimal lead time to manufacturing operations. However, disadvantages occur from multi-hour cycle times when used on complex MCM substrates with very high net counts and the resulting high operational costs and high number of required testers to provide the necessary capacity. This method does not require big investment on tooling, but it is a low throughput test method and cannot handle high volume production and is therefore not practical for large scale MCM production.
What is needed is a high throughput electrical test method for complex MCM's. Specifically, what is needed is a test method that utilizes a conventional Step and Repeat Cluster Probe Tester to test complex MCM's that do not have a normal step-able C4 pattern: MCM's comprising chips that have different sizes, sharing a common pitch but with divergent C4 footprints with non-repeating C4 patterns.